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AMD Alveo™ UL3524 Accelerator Card

The Alveo™ UL3524 is powered by a new Virtex UltraScale+™ FPGA built for electronic trading. The device features a breakthrough transceiver architecture to achieve less than 3ns latency for world-class trade execution, delivering 7X greater performance vs. previous FPGA technology.

  • General Specifications
  • FPGA Resources
  • 787K Look-up Tables (LUTS)
  • 1,722K registers
  • 1,680 DSP Slices
  • 256 Mb embedded memory (76 Mb Block RAM, 180 Mb UltraRAM)Transceivers
  • 8 GTYP transceivers (32.75 Gb/s)
  • 64 GTF ultra-low latencyOn-Board Memory
  • 16 GB DDR4, 64b +8b ECC at 2666 MT/s
  • 72 MB, 2×288 Mb QDR I+, 550 MhzInterfaces
  • 4x QSFP-DD (32 x 10/25G ports)Expansion Ports
  • Four ARF6 supports additional 32×10/25G ports to connect multiple cards
  • Two Pico-Clasp connectors for sidebandClock Synchronization
  • 1PPS In Configuration and Debug
  • 2 Gbit QSPI, JAG over Micro USBPCle® Interface
  • PCle Gen4 x8 (x16 physical connector)Form Factor
  • Full-height, ¾ Length (FHAL)
  • Single slotPower and Thermal
  • 180W Electrical
  • 125W TDP
  • Passive cooling

Support & Resources

Product Brief

Alveo ultra-low latency performance and hardware View Product Brief

Data Sheet

View accelerator card features for Alveo UL3524 View Data Sheet

Installation Guide

View installation guide for Alveo UL3524. View Installation Guide

Vivado™ Design Suite

Alveo™ accelerator cards support traditional FPGA design. Learn More

Alveo Example Designs

Download, reference designs from GitHub. Download Designs

Documentation

Explore all documentation for Alveo UL3524. Browse Documentation